1. Field of the Invention
The present invention relates to a clamping system for clamping a video signal, more particularly, to a clamping system that uses a charge-pump unit in association with a digital control mode to clamp the voltage level of the video signal, prior to the video signal being input to a programmable gain amplifier and an A/D converter, so as to reach a desired level.
2. Description of Related Art
When converting an analog video signal to a digital signal, the analog video signal is clamped to a desired level before being input to a programmable gain amplifier (PGA) and an analog/digital converter, because the analog video signal is usually far away from the required threshold level of the PGA and A/D converter. For example, such clamping technique is disclosed in U.S. Pat. No. 5,995,166 issued to Mitsubishi Denki Kabushiki Kaisha and U.S. Pat. No. 6,008,864 issued to Sony Corporation and Sony Electronics, Inc.
With reference to FIG. 8, which is a preferred embodiment of a clamping circuit taught by U.S. Pat. No. 5,995,166, the clamping circuit comprises a direct current electrical potential correcting circuit (100), a first processing circuit (200) and a second processing circuit (300). The DC electrical potential correcting circuit (100) has a non-inverted input terminal into which an analog video signal is input, an inverted input terminal connected to a capacitor (15) with a sample hold electrical potential, and an output terminal connected to the first processing circuit (200) and the second processing circuit (300).
Either of the first processing circuit (200) and the second processing circuit (300) has a first input node, a second input node and an output node. Their first input nodes are connected to the output terminal of the DC electrical potential correcting circuit (100). Their second input nodes are individually connected to a respective reference voltage Vsync and Vped, wherein both the Vsync and Vped are set based on the DC electrical potential in the composite video signal. The output nodes of the two processing circuits (200 and 300) are connected to the capacitor (15) with the sample hold electrical potential. The second processing circuit (200) is activated by receiving a clamp pulse input into a clamp pulse input node, whereby the capacitor (15) is alternately charged or discharged.
Based on the direct current electrical potential of the capacitor (15), the DC electrical potential correcting circuit (100) clamps the direct current electrical potential of the analog composite video signal.
Although the clamping circuit is able to clamp the direct current electrical potential of the analog composite video signal, the circuit does not consider the variation of the analog composite video signal so that the control flexibility is quite poor.